In the maintenance manual on page 7-13 in the Shift count subroutine section we find this: "right shifting, which is used in all multiplication and division, is done two places at at time.
So, I don't know why, but I do have a confirmation that I must learn how to multiple (and divide) in binary in a processor, before getting too far in the design of the arithmetic unit. Chapter 8 of the manual does some explanation on doing math. Soon...
Also in the manual is a lot of text description of the special purpose gating, by which I mean that there are many "exceptions" to the rule to handle all kinds of partial use of the registers. In many cases a partial result will be loaded into part of a register while the rest of the register reloads from the data it is currently holding.
i.e. bits 18-35 of the AR reload (recirculate) themselves while bits 12-17 load from one source and bits 0-11 load from another. (this is not an actual example, just a representative for instance).
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